久久久久久久久免费_久久久久久久久网站_久久久久久久久一区_久久久久久久网_一级免费在线_一级女人真人毛片免费看

THE PERSON: The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas KEY RESPONSIBILITIES: ?Work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project ?technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc PREFERRED EXPERIENCE: ?Master in Electrical Engineering, Computer Science or related ?Deep understanding on ASIC design verification flow ?RTL coding with Verilog/System Verilog ACADEMIC CREDENTIALS: MSEE with minimum of 6 years, or BSEE with minimum of 8 years experiences in digital ASIC/SOC design verification